DNN Wafer-Defect Detection at Intel

On Intel’s silicon wafer assembly line, validation time is money. As a machine learning engineering intern I developed a DNN computer-vision tool for wafer defect detection that reduced validation time, alongside data quality control for TEM metrology generation.

I also scripted a neural-network optimization system that automatically searched for ideal architectures and hyperparameters for a given application, and developed a repeatable methodology for standing up CUDA-enabled training environments on new machines.